1. Context

This document provides performance measures of the Enyx TCP core in multiple configurations.

The measures are automatically imported from simulations of the Enyx TCP core, and hardware measures result in the same results.

The document is split up as follows :

A description of the TCP Tx Cut-Through mode is provided in the TCP Reference Manual, which can be found online here

The TCP Rx Cut-Through feature is enabled by disabling the Safe Mode of the corresponding session, but also by disabling the TCP and IP checksum verifications for all sessions. Description of these registers can be found online at the following URL :

2. Resources & Working frequencies

Hereafter is a table showing TCP implementation results on our supported FPGA families. The compilations only include the TCP stack, therefore providing a maximum reachable frequency for each configuration. These results include the TCP resource usage averaged from 10 different runs along with the maximum frequency achieved on these 10 runs on either Vivado 2018.3 or Quartus 16.0 Standard, and the parameters applied to the tools are provided Section 5 Constraints applied to FPGA compiler tools for Resources and Working frequencies estimations.

These results are all done with TCP Retransmission memory instantiated as external memory (therefore it is not accounted for in the following section, since it is only the FPGA RAM blocks that are reported here).

  • Logic

    • in K ALM for Intel

    • in K LUT for Xilinx

  • Registers in K

  • Memory as block memory usage

    • M20k for Intel

    • 36k for Xilinx

Table 2.1 Resources summary for the Enyx TCP stack in Standard Edition.

Family

Device

Speed Grade

Nb of Sessions

Speed (Gbps)

Freq (MHz)

Logic

%

Registers

%

Memory

%

Arria 10

GX 1150

1

2

10

156

26349

7

48291

3

231

9

Arria 10

GX 1150

1

256

10

156

27567

7

50462

3

232

9

Arria 10

GX 1150

1

4096

10

156

27877

7

51376

4

833

31

Stratix V

GX A7

2

2

10

156

23399

10

44806

5

231

10

Stratix V

GX A7

2

256

10

156

24217

11

46342

5

232

10

Stratix V

GX A7

2

4096

10

156

24686

11

47223

6

833

33

Virtex US+

VU9P

2

2

10

156

37289

4

48931

3

87

5

Virtex US+

VU9P

2

256

10

156

38817

4

50605

3

88

5

Virtex US+

VU9P

2

4096

10

156

38634

4

51473

3

95

5

Virtex US+

VU9P

2

2

25

250

50969

5

71023

4

35

2

Virtex US+

VU9P

2

256

25

250

50750

5

67471

3

92

5

Virtex US+

VU9P

2

4096

25

250

50609

5

68590

3

174

9

Virtex US+

VU9P

3

2

10

156

37291

4

48933

3

87

5

Virtex US+

VU9P

3

256

10

156

38815

4

50605

3

88

5

Virtex US+

VU9P

3

4096

10

156

38627

4

51473

3

95

5

Virtex US+

VU9P

3

2

25

250

50893

5

71010

4

35

2

Virtex US+

VU9P

3

256

25

250

50732

5

67430

3

92

5

Virtex US+

VU9P

3

4096

25

250

50611

5

68577

3

174

9

Table 2.2 Resources summary for the Enyx TCP stack in Financial Edition.

Family

Device

Speed Grade

Nb of Sessions

Speed (Gbps)

Freq (MHz)

Logic

%

Registers

%

Memory

%

Arria 10

GX 1150

1

2

10

250

23438

6

43968

3

169

7

Arria 10

GX 1150

1

64

10

250

26605

7

50525

3

169

7

Stratix V

GX A7

2

2

10

250

22415

10

42819

5

170

7

Stratix V

GX A7

2

64

10

250

25752

11

49475

6

171

7

Virtex US+

VU9P

2

2

10

250

33563

3

46198

2

78

4

Virtex US+

VU9P

2

64

10

250

38623

4

52242

3

78

4

Virtex US+

VU9P

2

2

10

322

33630

3

46576

2

78

4

Virtex US+

VU9P

2

64

10

322

38655

4

52585

3

78

4

Virtex US+

VU9P

2

2

10

350

33707

3

46766

2

78

4

Virtex US+

VU9P

2

64

10

350

38720

4

52654

3

78

4

Virtex US+

VU9P

2

2

10

380

33787

3

46605

2

78

4

Virtex US+

VU9P

2

64

10

380

38793

4

52762

3

78

4

Virtex US+

VU9P

3

2

10

250

33564

3

46150

2

78

4

Virtex US+

VU9P

3

64

10

250

38606

4

52139

3

78

4

Virtex US+

VU9P

3

2

10

322

33601

3

46421

2

78

4

Virtex US+

VU9P

3

64

10

322

38636

4

52439

3

78

4

Virtex US+

VU9P

3

2

10

350

33664

3

46567

2

78

4

Virtex US+

VU9P

3

64

10

350

38675

4

52643

3

78

4

Virtex US+

VU9P

3

2

10

380

33713

3

46695

2

78

4

Virtex US+

VU9P

3

64

10

380

38740

4

52653

3

78

4

A Recommended Frequency is provided for each use case, showing reasonable working frequencies for the Enyx TCP stack (Financial Edition) in a typical scenario, along with the best frequency achieved on the specified target amongst all runs.

Table 2.3 Recommended clock frequency for the Enyx TCP stack in Financial Edition.

Family

Device

Speed Grade

Speed (Gbps)

Freq (MHz)

Best Freq Achieved (MHz)

Arria 10

GX 1150

1

10

250

264

Stratix V

GX A7

2

10

250

296

Virtex US+

VU9P

2

10

322

396

Virtex US+

VU9P

3

10

350

397

3. Latency Testing

In order to measure the latency of the Enyx TCP Stack, the following test is performed:

  • For Rx latency :

    • Packets are sent out from a MAC core to the Enyx TCP stack, one by one, from 1 to 2048 Bytes with a step of 8 Bytes.

    • Packets are immediately timestamped when they enter the TCP stack, at the Start of Packet (SoP).

    • As soon as the packets are received on the Enyx TCP Rx User Out interface, a second timestamp is performed, at the Start of Packet (SoP).

    • Both timestamps are compared and provides the TCP Rx latency for each packet size.

    _images/TCP_perfs_latency_rx.svg

    Figure 3.1 Enyx TCP 10G RX Latency Testing Scenario

  • For Tx latency :

    • Packets are pushed to the Enyx TCP Tx User In interface, one by one, from 1 to 2048 Bytes with a step of 8 Bytes.

    • Packets are immediately timestamped when they enter the TCP stack, at the Start of Packet (SoP).

    • As soon as the packets are received on the Enyx MAC core, a second timestamp is performed, at the Start of Packet (SoP).

    • Both timestamps are compared and provides the TCP Tx latency for each packet size.

    _images/TCP_perfs_latency_tx.svg

    Figure 3.2 Enyx TCP 10G TX Latency Testing Scenario

Latencies are all measured from Start-of-Packet (SoP) to Start-of-Packet (SoP).

All latency tests have been performed with the following TCP parameters :

  • MM_CLK_RESYNCH=1

  • MM_ADDR_WIDTH=10

  • MTU=9000

  • MAC_DATA_WIDTH=64 for 1G and 10G tests, 128 for 25G tests.

  • TCP_STACK_DISABLE=0

  • TCP_ENABLE_INSTANT_ACK=1

  • TCP_INTERFACE_COUNT=1

  • TCP_USR_DATA_WIDTH=128

  • TCP_ICMP_ARP_SERVER_DISABLE=0

  • TCP_RX_FIFO_PACKET_COUNT=4

  • TCP_RX_OUTPUT_PIPE_COUNT=0

  • TCP_TX_OUTPUT_PIPE_COUNT=0

  • TCP_SESSION_COUNT=16

  • TCP_MEM_EXTERNAL=0

  • TCP_MEM_EXTERNAL_LATENCY=2

  • TCP_MEM_CLK_DIFF_FROM_SYS_CLK=0

  • TCP_MEM_ADDR_WIDTH=16

  • TCP_MEM_DATA_WIDTH=128

  • TCP_PUSH_BIT_VALUE=0

  • TCP_TX_DROP_IF_NOT_ESTABLISHED=0

  • TCP_SUPPORT_OOS_SEQNUM=0

  • TCP_CONF_BUS_LOW_FOOTPRINT=0

  • TCP_AUTO_RESET_TX_STALLED_SESSION=0

  • TCP_EMI_STATUS_DISABLE=1

  • TCP_EMI_CREDIT_DISABLE=1

3.1. Latency Summary

Table 3.1 Enyx TCP Latency Summary table for Standard Edition

TCP Payload Size (Bytes)

1

8

16

32

64

128

256

512

1024

2048

10G - 156 MHz - RTT (ns)

242

242

249

255

294

371

525

833

1448

2679

  • TX (ns)

57

57

57

57

70

96

147

250

455

865

  • RX (ns)

185

185

192

198

224

275

378

583

993

1814

25G - 250 MHz - RTT (ns)

168

168

168

168

180

212

276

416

708

1292

  • TX (ns)

68

68

68

68

72

88

120

184

312

568

  • RX (ns)

100

100

100

100

108

124

156

232

396

724

Table 3.2 Enyx TCP Latency Summary table for Financial Edition

TCP Payload Size (Bytes)

1

8

16

32

64

128

256

512

1024

2048

10G - 250 MHz - RTT (ns)

108

112

116

128

160

228

360

632

1168

2244

  • TX (ns)

24

24

24

24

32

48

80

144

272

528

  • RX (ns)

84

88

92

104

128

180

280

488

896

1716

10G - 250 MHz - CT - RTT (ns)

100

104

108

112

112

112

112

112

112

112

  • Cut-Through - TX (ns)

24

24

24

24

24

24

24

24

24

24

  • Cut-Through - RX (ns)

76

80

84

88

88

88

88

88

88

88

10G - 322 MHz - RTT (ns)

92

95

101

111

142

207

335

589

1099

2113

  • TX (ns)

18

18

18

18

24

37

62

111

211

409

  • RX (ns)

74

77

83

93

118

170

273

478

888

1704

10G - 322 MHz - CT - RTT (ns)

86

89

95

98

98

98

98

98

98

98

  • Cut-Through - TX (ns)

18

18

18

18

18

18

18

18

18

18

  • Cut-Through - RX (ns)

68

71

77

80

80

80

80

80

80

80

10G - 350 MHz - RTT (ns)

88

91

97

108

139

202

328

576

1079

2079

  • TX (ns)

17

17

17

17

22

34

57

102

194

377

  • RX (ns)

71

74

80

91

117

168

271

474

885

1702

10G - 350 MHz - CT - RTT (ns)

82

85

91

97

97

97

97

97

97

97

  • Cut-Through - TX (ns)

17

17

17

17

17

17

17

17

17

17

  • Cut-Through - RX (ns)

65

68

74

80

80

80

80

80

80

80

3.2. 10G Tx

_images/TCP_10G_TX_Latency.svg

Figure 3.3 Enyx TCP 10G TX Latency diagram

Table 3.3 Enyx TCP 10G TX Latency table for Standard Edition

TCP Payload Size (Bytes)

1

8

16

32

64

128

256

512

1024

2048

156 MHz (ns)

57

57

57

57

70

96

147

250

455

865

Table 3.4 Enyx TCP 10G TX Latency table for Financial Edition

TCP Payload Size (Bytes)

1

8

16

32

64

128

256

512

1024

2048

250 MHz (ns)

24

24

24

24

32

48

80

144

272

528

322 MHz (ns)

18

18

18

18

24

37

62

111

211

409

350 MHz (ns)

17

17

17

17

22

34

57

102

194

377

3.3. 10G Tx Cut-Through

_images/TCP_10G_TX_Latency_CutThrough.svg

Figure 3.4 Enyx TCP 10G TX Cut-Through Latency diagram

Table 3.5 Enyx TCP 10G TX Cut-Through Latency table for Financial Edition

TCP Payload Size (Bytes)

1

8

16

32

64

128

256

512

1024

2048

250 MHz (ns)

24

24

24

24

24

24

24

24

24

24

322 MHz (ns)

18

18

18

18

18

18

18

18

18

18

350 MHz (ns)

17

17

17

17

17

17

17

17

17

17

3.4. 10G Rx

_images/TCP_10G_RX_Latency.svg

Figure 3.5 Enyx TCP 10G RX Latency diagram

Table 3.6 Enyx TCP 10G RX Latency table for Standard Edition

TCP Payload Size (Bytes)

1

8

16

32

64

128

256

512

1024

2048

156 MHz (ns)

185

185

192

198

224

275

378

583

993

1814

Table 3.7 Enyx TCP 10G RX Latency table for Financial Edition

TCP Payload Size (Bytes)

1

8

16

32

64

128

256

512

1024

2048

250 MHz (ns)

84

88

92

104

128

180

280

488

896

1716

322 MHz (ns)

74

77

83

93

118

170

273

478

888

1704

350 MHz (ns)

71

74

80

91

117

168

271

474

885

1702

3.5. 10G Rx Cut-Through

_images/TCP_10G_RX_Latency_CutThrough.svg

Figure 3.6 Enyx TCP 10G RX Cut-Through Latency diagram

Table 3.8 Enyx TCP 10G RX Cut-Through Latency table for Financial Edition

TCP Payload Size (Bytes)

1

8

16

32

64

128

256

512

1024

2048

250 MHz (ns)

76

80

84

88

88

88

88

88

88

88

322 MHz (ns)

68

71

77

80

80

80

80

80

80

80

350 MHz (ns)

65

68

74

80

80

80

80

80

80

80

3.6. 25G Tx

_images/TCP_25G_TX_Latency.svg

Figure 3.7 Enyx TCP 25G TX Latency diagram

Table 3.9 Enyx TCP 25G TX Latency table for Standard Edition

TCP Payload Size (Bytes)

1

8

16

32

64

128

256

512

1024

2048

250 MHz (ns)

68

68

68

68

72

88

120

184

312

568

3.7. 25G Rx

_images/TCP_25G_RX_Latency.svg

Figure 3.8 Enyx TCP 25G RX Latency diagram

Table 3.10 Enyx TCP 25G RX Latency table for Standard Edition

TCP Payload Size (Bytes)

1

8

16

32

64

128

256

512

1024

2048

250 MHz (ns)

100

100

100

100

108

124

156

232

396

724

4. Bandwidth Testing

In order to measure the bandwidth of the Enyx TCP Stack, the following test is performed:

  • For Rx bandwidth :

    • 100 Packets are sent out from a MAC core to the Enyx TCP stack for each packet sizes from 1 to 512 Bytes with a step of 16 Bytes.

    • The packets are sent out at the maximum data rate possible (so for the Enyx TCP Bandwidth 10G Rx test we will send out the packets at a rate of 10Gbps, for 25G they are sent out at 25Gbps…).

    • If the TCP stack drops any of the 100 packets, then the test for this packet size fails, and it is repeated with a slower bandwidth.

    • As soon as the TCP stack doesn’t drop any of the packets, then the test for this packet size succeeds, and the current bandwidth is recorded.

    _images/TCP_perfs_bandwidth_rx.svg

    Figure 4.1 Enyx TCP 10G RX Bandwidth Testing Scenario

  • For Tx bandwidth :

    • 100 Packets are pushed to the Enyx TCP stack on the TCP Tx User Interface for each packet sizes from 1 to 512 Bytes with a step of 16 Bytes.

    • The packets are sent out at the maximum data rate possible ( TCP_USR_DATA_WIDTH * CLOCK).

    • The output of the TCP stack to the MAC goes to a bandwidth limiter module, whose sole purpose is to limite it’s own bandwidth capability to the selected ethernet speed (so for the Enyx TCP Bandwidth 10G Tx test, the bandwidth limiter module will operate at maximum speed of 10Gbps, for 25G it will operate at 25Gbps…)

    • The Tx bandwidth is directly measured between the TCP stack to the bandwidth limiter module.

    _images/TCP_perfs_bandwidth_tx.svg

    Figure 4.2 Enyx TCP 10G TX Bandwidth Testing Scenario

All bandwidth tests have been performed with the following TCP parameters :

  • MM_CLK_RESYNCH=1

  • MM_ADDR_WIDTH=10

  • MTU=1500

  • MAC_DATA_WIDTH=64 for 1G and 10G tests, 128 for 25G tests.

  • TCP_STACK_DISABLE=0

  • TCP_ENABLE_INSTANT_ACK=1

  • TCP_INTERFACE_COUNT=1

  • TCP_USR_DATA_WIDTH=128

  • TCP_ICMP_ARP_SERVER_DISABLE=0

  • TCP_RX_FIFO_PACKET_COUNT=4

  • TCP_RX_OUTPUT_PIPE_COUNT=0

  • TCP_TX_OUTPUT_PIPE_COUNT=0

  • TCP_SESSION_COUNT=16

  • TCP_MEM_EXTERNAL=0

  • TCP_MEM_EXTERNAL_LATENCY=2

  • TCP_MEM_CLK_DIFF_FROM_SYS_CLK=0

  • TCP_MEM_ADDR_WIDTH=16

  • TCP_MEM_DATA_WIDTH=128

  • TCP_PUSH_BIT_VALUE=0

  • TCP_TX_DROP_IF_NOT_ESTABLISHED=0

  • TCP_SUPPORT_OOS_SEQNUM=0

  • TCP_CONF_BUS_LOW_FOOTPRINT=0

  • TCP_AUTO_RESET_TX_STALLED_SESSION=0

  • TCP_EMI_STATUS_DISABLE=1

  • TCP_EMI_CREDIT_DISABLE=1

4.1. Bandwidth Summary

Table 4.1 Enyx TCP Bandwidth Summary table for Standard Edition Tx

TCP Payload Size (Bytes)

1

16

32

64

128

256

512

10G - 156 MHz - TX (Mbit/s)

10000

10000

10000

10000

10000

10000

10000

25G - 250 MHz - TX (Mbit/s)

11173

13950

16722

22246

25000

25000

25000

Table 4.2 Enyx TCP Bandwidth Summary table for Standard Edition Rx

TCP Payload Size (Bytes)

1

16

32

64

128

256

512

10G - 156 MHz - RX (Mbit/s)

10000

10000

10000

10000

10000

10000

10000

25G - 250 MHz - RX (Mbit/s)

18374

22562

23750

23750

23750

23750

23750

Table 4.3 Enyx TCP Latency Summary table for Financial Edition Tx

TCP Payload Size (Bytes)

1

16

32

64

128

256

512

10G - 250 MHz - TX (Mbit/s)

10000

10000

10000

10000

10000

10000

10000

10G - 250 MHz - CT - TX (Mbit/s)

10000

10000

10000

10000

10000

10000

10000

10G - 322 MHz - TX (Mbit/s)

10000

10000

10000

10000

10000

10000

10000

10G - 322 MHz - CT - TX (Mbit/s)

10000

10000

10000

10000

10000

10000

10000

10G - 350 MHz - TX (Mbit/s)

10000

10000

10000

10000

10000

10000

10000

10G - 350 MHz - CT - TX (Mbit/s)

10000

10000

10000

10000

10000

10000

10000

Table 4.4 Enyx TCP Latency Summary table for Financial Edition Rx

TCP Payload Size (Bytes)

1

16

32

64

128

256

512

10G - 250 MHz - RX (Mbit/s)

10000

10000

10000

10000

10000

10000

10000

10G - 250 MHz - CT - RX (Mbit/s)

10000

10000

10000

10000

10000

10000

10000

10G - 322 MHz - RX (Mbit/s)

10000

10000

10000

10000

10000

10000

10000

10G - 322 MHz - CT - RX (Mbit/s)

10000

10000

10000

10000

10000

10000

10000

10G - 350 MHz - RX (Mbit/s)

10000

10000

10000

10000

10000

10000

10000

10G - 350 MHz - CT - RX (Mbit/s)

10000

10000

10000

10000

10000

10000

10000

4.2. 10G Tx

_images/TCP_10G_TX_Bandwidth.svg

Figure 4.3 Enyx TCP 10G TX Bandwidth diagram

Table 4.5 Enyx TCP 10G TX Bandwidth table for Standard Edition

TCP Payload Size (Bytes)

1

16

32

64

128

256

512

156 MHz (Mbit/s)

10000

10000

10000

10000

10000

10000

10000

Table 4.6 Enyx TCP 10G TX Bandwidth table for Financial Edition

TCP Payload Size (Bytes)

1

16

32

64

128

256

512

250 MHz (Mbit/s)

10000

10000

10000

10000

10000

10000

10000

322 MHz (Mbit/s)

10000

10000

10000

10000

10000

10000

10000

350 MHz (Mbit/s)

10000

10000

10000

10000

10000

10000

10000

4.3. 10G Tx Cut-Through

_images/TCP_10G_TX_Bandwidth_CutThrough.svg

Figure 4.4 Enyx TCP 10G TX Cut-Through Bandwidth diagram

Table 4.7 Enyx TCP 10G TX Cut-Through Bandwidth table for Financial Edition

TCP Payload Size (Bytes)

1

16

32

64

128

256

512

250 MHz (Mbit/s)

10000

10000

10000

10000

10000

10000

10000

322 MHz (Mbit/s)

10000

10000

10000

10000

10000

10000

10000

350 MHz (Mbit/s)

10000

10000

10000

10000

10000

10000

10000

4.4. 10G Rx

_images/TCP_10G_RX_Bandwidth.svg

Figure 4.5 Enyx TCP 10G RX Bandwidth diagram

Table 4.8 Enyx TCP 10G RX Bandwidth table for Standard Edition

TCP Payload Size (Bytes)

1

16

32

64

128

256

512

156 MHz (Mbit/s)

10000

10000

10000

10000

10000

10000

10000

Table 4.9 Enyx TCP 10G RX Bandwidth table for Financial Edition

TCP Payload Size (Bytes)

1

16

32

64

128

256

512

250 MHz (Mbit/s)

10000

10000

10000

10000

10000

10000

10000

322 MHz (Mbit/s)

10000

10000

10000

10000

10000

10000

10000

350 MHz (Mbit/s)

10000

10000

10000

10000

10000

10000

10000

4.5. 10G Rx Cut-Through

_images/TCP_10G_RX_Bandwidth_CutThrough.svg

Figure 4.6 Enyx TCP 10G RX Cut-Through Bandwidth diagram

Table 4.10 Enyx TCP 10G RX Cut-Through Bandwidth table for Financial Edition

TCP Payload Size (Bytes)

1

16

32

64

128

256

512

250 MHz (Mbit/s)

10000

10000

10000

10000

10000

10000

10000

322 MHz (Mbit/s)

10000

10000

10000

10000

10000

10000

10000

350 MHz (Mbit/s)

10000

10000

10000

10000

10000

10000

10000

4.6. 25G Tx

_images/TCP_25G_TX_Bandwidth.svg

Figure 4.7 Enyx TCP 25G TX Bandwidth diagram

Table 4.11 Enyx TCP 25G TX Bandwidth table for Standard Edition

TCP Payload Size (Bytes)

1

16

32

64

128

256

512

250 MHz (Mbit/s)

11173

13950

16722

22246

25000

25000

25000

4.7. 25G Rx

_images/TCP_25G_RX_Bandwidth.svg

Figure 4.8 Enyx TCP 25G RX Bandwidth diagram

Table 4.12 Enyx TCP 25G RX Bandwidth table for Standard Edition

TCP Payload Size (Bytes)

1

16

32

64

128

256

512

250 MHz (Mbit/s)

18374

22562

23750

23750

23750

23750

23750

5. Constraints applied to FPGA compiler tools for Resources and Working frequencies estimations

Hereafter are the constraints that are provided to the default FPGA compiler tools for the Resources and Working frequencies estimations.

5.1. Stratix V targets

regexp {[\.0-9]+} $quartus(version) quartus_version
regexp {Full|Standard|Pro} $quartus(version) quartus_edition
set quartus_version_major [lindex [regexp -all -inline {[0-9]+} $quartus_version] 0]
set quartus_version_minor [lindex [regexp -all -inline {[0-9]+} $quartus_version] 1]


set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS ON
set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF
set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT ON

if {$quartus_version_major >= 15} {
    set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
    set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING "FORCE ALL USED TILES TO HIGH SPEED"
    set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION AUTO
}
if {($quartus_version_major == 16 && $quartus_version_minor == 0) || ($quartus_version_major < 16)} {
    set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
    set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
    set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
    set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
    set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
    set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON
    set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
}

5.2. Arria 10 targets

regexp {[\.0-9]+} $quartus(version) quartus_version
regexp {Full|Standard|Pro} $quartus(version) quartus_edition
set quartus_version_major [lindex [regexp -all -inline {[0-9]+} $quartus_version] 0]
set quartus_version_minor [lindex [regexp -all -inline {[0-9]+} $quartus_version] 1]

set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS ON
set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE ON
set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT ON
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING "FORCE ALL USED TILES TO HIGH SPEED"
set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION AUTO
set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS OFF
set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS OFF
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
set_global_assignment -name ALLOW_REGISTER_MERGING ON
set_global_assignment -name ALLOW_REGISTER_RETIMING ON
set_global_assignment -name ALM_REGISTER_PACKING_EFFORT LOW
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
set_global_assignment -name ECO_OPTIMIZE_TIMING ON
set_global_assignment -name AUTO_DELAY_CHAINS ON
set_global_assignment -name AUTO_GLOBAL_CLOCK ON

if {$quartus_version_major >= 19} {
    set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT WITH MAXIMUM PLACEMENT EFFORT"
    set_global_assignment -name GLOBAL_PLACEMENT_EFFORT "MAXIMUM EFFORT"
} elseif {$quartus_version_major >= 16} {
        set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE"
        set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
        set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
        set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
        set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
        set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA OFF
        set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA OFF
        set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
}

5.3. Virtex UltraScale+ (-2 speed grade) targets

################ FPGA ####################
set_property part xcvu9p-flgb2104-2-e [current_project]

set_property STEPS.SYNTH_DESIGN.ARGS.FANOUT_LIMIT 400 [get_runs synth_*]
set_property STEPS.SYNTH_DESIGN.ARGS.FSM_EXTRACTION one_hot [get_runs synth_*]
set_property STEPS.SYNTH_DESIGN.ARGS.KEEP_EQUIVALENT_REGISTERS true [get_runs synth_*]
set_property STEPS.SYNTH_DESIGN.ARGS.RESOURCE_SHARING off [get_runs synth_*]
set_property STEPS.SYNTH_DESIGN.ARGS.NO_LC true [get_runs synth_*]
set_property STEPS.SYNTH_DESIGN.ARGS.SHREG_MIN_SIZE 5 [get_runs synth_*]

set_property strategy Performance_BalanceSLLs [get_runs impl_*]

5.4. Virtex UltraScale+ (-3 speed grade) targets

################ FPGA ####################
set_property part xcvu9p-flgb2104-3-e [current_project]

set_property STEPS.SYNTH_DESIGN.ARGS.FANOUT_LIMIT 400 [get_runs synth_*]
set_property STEPS.SYNTH_DESIGN.ARGS.FSM_EXTRACTION one_hot [get_runs synth_*]
set_property STEPS.SYNTH_DESIGN.ARGS.KEEP_EQUIVALENT_REGISTERS true [get_runs synth_*]
set_property STEPS.SYNTH_DESIGN.ARGS.RESOURCE_SHARING off [get_runs synth_*]
set_property STEPS.SYNTH_DESIGN.ARGS.NO_LC true [get_runs synth_*]
set_property STEPS.SYNTH_DESIGN.ARGS.SHREG_MIN_SIZE 5 [get_runs synth_*]