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nxUDP – Standard Edition
10G & 25G UDP/IP + MAC IP Cores for FPGAs
The world’s most reliable and mature full hardware UDP/IP and MAC IP Cores
Bring the best-in-class network connectivity to your hardware code and algorithms with Enyx rock-solid and acclaimed Ethernet IP Cores. Minimize time-to-market with our full RTL implementation and support. Stay always at the forefront of technology with our frequent updates with the latest improvements and optimizations.
The nxUDP – Standard Edition overview:
Available FPGA providers:

High Performance Computing

Technology manufacturers

Telecom operators

Universities & research Labs
Key Points
- 10G & 25G Ethernet connectivity. Maximum bandwidth delivered with low latency
- Full RTL Layers 2, 3 and 4, which include Enyx proprietary full-hardware UDP/IP, ARP, ICMP, IGMP and MAC implementations
- Easy to use standardized Avalon and AXI-4 interfaces
- Support of multiple instances per FPGA
- Each connection can be configured dynamically in server or client mode
- Support for Unicast and Multicast transmit/receive
Compliant with:
Management of layers 1, 2, 3 and 4 (OSI Model), compliant with:
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Layer 1: Ethernet (IEEE802.3)
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Layer 2: Ethernet (IEEE802.3), ARP (RFC 826)
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Layer 3: IPv4 (RFC 791), ICMP (RFC 792) and IGMPv2 (RFC 2236)
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Layer 4: TCP (RFC 793), UDP (RFC 768) or UDP+PGM (RFC 3208)

Technical Specifications
Layers 1 and 2: Physical and Data Link
PHY Interface
10G – XGMII interface (72-bit @ 156.25 MHz) to integrated XAUI PHY or 10GBase-R with PMA-PCS
25G – XXVGMII interface (72-bit @ 390.625 MHz) to integrated XXVAUI or 25GBase-R with PMA-PCS.
Raw MAC Stream Interface (access to MAC in promiscuous/transparent mode)
10G – 64-bit wide @ 156.25 MHz
25G – 128-bit wide @ 195.3125 MHz
Customizable MTU (Maximum Transmission Unit)
– Up to 9000 bytes payload to support from standard to jumbo frames.
Supported FPGA platforms:
Layers 3 and 4: Network and Transport
ICMP and ARP protocols
– Support for ARP static tables.
Multiple Interfaces
– Up to 8 logical interfaces per instance, each of them with unique IPv4 and MAC addresses, VLAN ID, gateway and mask.
Avalon/AXI-4 Streaming Interface
10G – 128-bit wide @ 156.25 MHz
25G – 128-bit wide @ 195.3125 MHz
Configuration and management interface
– 32-bit Avalon-MM/AXI-4 lite slave control interface.
– Status and statistics available for monitoring at MAC, TCP and UDP session level.
UDP/IP specifications
Up to 256 UDP sessions
IGMPv2 protocol
– Support for Membership Report/Leave message generation (for UDP multicast groups).
– Support for Membership Query message reception.
Supports Unicast and Multicast transmit/receive
Enyx certified board partners:
Package contents
nxUDP IP Core
– Libraries for functional simulation
– Synthesizable VHDL and Verilog RTL (encrypted) for synthesis/implementation
nxUDP Test bench
– Simulation libraries
Client-Server Reference Designs
– Simulation environment and scripts
– Quartus II and Vivado Synthesis/implementation project for supported partner’s
– Integrated support for 10GBase-R or XAUI External PHY to QSFP/SFP+ module
Complete Documentation
– nxUDP user’s manual
– Getting started guide
Technical Support and Maintenance Updates
– 1 year of technical support
– 1 year of IP updates
Available reference designs
Xilinx Virtex UltraScale+
Xilinx Series 7
Downloads
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