nxTCP – Standard Edition

10G & 25G TCP/IP + MAC IP Cores for FPGAs

The world’s most reliable and mature full hardware TCP/IP and MAC IP Cores

 

Bring the best-in-class network connectivity to your hardware design with Enyx rock-solid and acclaimed Ethernet IP Cores. Minimize time-to-market with our full RTL implementation and support. Stay always at the forefront of technology with our frequent updates with the latest improvements and optimizations.

 

The nxTCP – Standard Edition overview:

schema nxTCP Standard edition

 

Performance Reports

Consult our latest latency figures

 

view report

Key Points

TCP/IP + MAC IP Cores

 

  • 10G & 25G Ethernet connectivity. Maximum bandwidth delivered with low latency
  • Full RTL Layers 2, 3 and 4, which include Enyx proprietary full-hardware TCP/IP, ARP, ICMP and MAC implementations
  • Easy to use standardized Avalon and AXI-4 interfaces
  • Multiple instances per FPGA and multiple logical interfaces per instance, each of them with a unique IPv4, MAC address, VLAN ID, Gateway and Mask
  • Up to 32768 TCP simultaneous sessions per instance, each of them configurable dynamically in server or client mode

 

Available FPGA providers:

Technical Specifications


 

Layers 1 and 2: Physical and Data Link

 

PHY Interface

10G – XGMII interface (72-bit @ 156.25 MHz) to integrated XAUI PHY or 10GBase-R with PMA-PCS
25G – XXVGMII interface (72-bit @ 390.625 MHz) to integrated XXVAUI or 25GBase-R with PMA-PCS.

 

Raw MAC Stream Interface (access to MAC in promiscuous/transparent mode)

10G – 64-bit wide @ 156.25 MHz
25G – 128-bit wide @ 195.3125 MHz

 

Customizable MTU (Maximum Transmission Unit)

  • Up to 9000 bytes payload to support from standard to jumbo frames

Supported FPGA platforms:


Layers 3 and 4: Network and Transport

 

ICMP and ARP protocols

  • Support for ARP static tables

 

Multiple Interfaces

  • Up to 8 logical interfaces per instance, each of them with unique IPv4 and MAC addresses, VLAN ID, gateway and mask

 

Avalon/AXI-4 Streaming Interface

10G – 128-bit wide @ 156.25 MHz
25G – 128-bit wide @ 195.3125 MHz

 

Configuration and management interface

  • 32-bit Avalon-MM/AXI-4 lite slave control interface.
  • Status and statistics available for monitoring at MAC, TCP and UDP session level.

 


TCP/IP specifications

 

User configurable options for each session

  • Configurable at runtime in client or server mode
  • VLAN Priority, with insertion of PCP and DEI fields at emission
  • MSS
  • Window Scale Factor
  • Timestamp

 

Retransmission and reception buffers

  • Customizable buffer size (depth and width)
  • Internal or External memory support (DDRx, QDRx, etc)

 

Congestion Control

  • Compliant with TCP New Reno algorithm.
  • Computed for each session

 

Flow Control

  • Sliding window mechanism
  • Packet reordering

 

Up to 32768 TCP simultaneous sessions per TCP instance

 

Fast Retransmit

Enyx certified board partners:


Package contents

 

nxTCP IP Core
– Libraries for functional simulation
– Synthesizable VHDL and Verilog RTL (encrypted) for synthesis/implementation

 

nxTCP Testbench
– Simulation libraries

 

Client-Server Reference Designs
– Simulation environment and scripts
– Quartus II and Vivado Synthesis/implementation project for supported partner’s
– Integrated support for 10GBase-R or XAUI External PHY to QSFP/SFP+ module

 

Complete Documentation

– nxTCP user’s manual
– Getting started guide

 

Technical Support and Maintenance Updates
– 1 year of technical support
– 1 year of IP updates