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The industry’s most reliable & mature full hardware, ultra-low latency TCP, MAC + PCS IP cores

Bring the best-in-class ultra-low latency network connectivity to your hardware design with Enyx rock-solid and acclaimed Ethernet IP Cores. Minimize time-to-market with our full RTL implementation and support. Stay always at the forefront of technology with our frequent updates with the latest latency improvements and optimizations.

The nxTCP – Financial Edition overview:

Key Points

TCP/IP + MAC + PCS IP CORES

• Best-in-class ultra-low latency from wire to user’s logic.
• 10G Ethernet connectivity. Maximum bandwidth delivered.
• Full RTL Layers 1, 2, 3 and 4, which include Enyx proprietary ultra-low latency full hardware TCP/IP, ARP, ICMP, MAC and PCS implementations.
• Clock configurable at up to 250 MHz, for improved latency results.
• Easy to use standardized Avalon and AXI-4 interfaces.
• Multiple instances per FPGA and multiple logical interfaces per instance, each of them with a unique IPv4, MAC address, VLAN ID, Gateway and Mask.
• Up to 128 TCP sessions per instance, each of them configurable dynamically in server or client mode.

Technical Specifications

TCP Management per session
– Up to 128 simultaneous sessions
– Client or server mode configurable at runtime

User Configurable TCP Options
– VLAN Priority, with insertion of PCP and DEI fields at emission
– MSS
– Window Scale Factor
– Timestamp

Customizable MTU (Maximum Transmission Unit)
– Up to 9000 bytes payload to support from standard to jumbo frames

MAC in Promiscuous mode (transparent)
– Access to MAC raw TX/RX interface

ICMP and ARP protocol support

Multiple Interface
– Up to 8 logical interfaces per instance
– Linked to any session
– VLAN configurable per interface

Avalon/AXI-4 Streaming
– 128-bit wide interface running at 250 MHz for TCP/IP client port
– 64-bit wide interface running at 250 MHz for MAC client port (TCP/IP bypass)

IP configuration/management
– 32-bit Avalon-MM/AXI- 4 lite slave control interface for MAC and TCP
– Status and statistics available for monitoring at MAC or TCP session level

Customizable TCP retransmission buffer
– Customizable buffer size (depth and width)
– Customizable Internal or External memory support (DDRx, QDRx, …) depending configuration on performance and FPGA size requirements

PHY Interface
– PMA Parallel Data between PCS and vendor PMA (PMA Direct Mode for Altera
– MII 64-bit Streaming Interface between PCS and MAC

Package contents

nxTCP IP Core
– Libraries for functional simulation
– Synthesizable VHDL and Verilog RTL (encrypted) for synthesis/implementation

nxTCP Testbench
– Simulation libraries

Client-Server Reference Designs
– Simulation environment and scripts
– Quartus II and Vivado Synthesis/implementation project for supported partner’s boards

Complete Documentation
– User’s manual
– Getting started guide

Technical Support and Maintenance Updates
– 1 year of technical support
– 1 year of IP updates

Available reference designs

Xilinx Virtex UltraScale +

• BittWare XUPP3R
• Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit

Intel Stratix V

• BittWare S5-PCIe-HQ

Intel Arria 10

• ReFLEX CES XpressGXA10-LP1150