nxMAC + PCS – Financial Edition

10G Ultra-low latency MAC + PCS IP core for FPGAs

The world’s most reliable and mature full hardware ultra-low latency MAC and PCS IP Cores.

 

Bring the best-in-class ultra-low latency network connectivity to your hardware code and algorithms with Enyx rock-solid and acclaimed Ethernet IP Cores.

 

Minimize time-to-market with our full RTL implementation and support. Stay always at the forefront of technology with our frequent updates with the latest latency improvements and optimizations.

 

The nxMAC + PCS – Financial Edition overview:

schema nxMacs-nxPCS

Performance Reports

Consult our latest latency figures

 

 

view report


Key Points

MAC + PCS IP Cores

 

  • Best-in-class latency from the wire to the user’s own logic.
  • 10G Ethernet connectivity. Maximum bandwidth delivered.
  • Full RTL Enyx proprietary ultra-low latency hardware MAC and PCS implementations.
  • Clock configurable at up to 250 MHz, for improved latency results.
  • Easy to use standardized Avalon and AXI-4 interfaces.
  • Multiple instances per FPGA and multiple logical interfaces per instance, each of them with a unique MAC address.

 

 

Available FPGA Providers:

 

Technical Specifications


 

Layers 1 and 2: Physical and Data Link

 

Management of layers 1 and 2 (OSI Model), compliant with:

  • Layer 1: IEEE802.3
  • Layer 2: IEEE802.3, ARP (Address Resolution Protocol)

 

Multiple Interface

  • Up to 8 logical interfaces per instance

 

Avalon/AXI-4 Streaming

  • 64-bit wide interface running at 250 MHz for MAC client port

 

IP configuration/management

  • 32-bit Avalon-MM/AXI- 4 lite slave control interface for MAC configuration
  • Status and statistics available for monitoring at MAC session level

 

PHY Interface

  • PMA Parallel Data between PCS and vendor PMA (PMA Direct Mode for Altera
  • MII 64-bit Streaming Interface between PCS and MAC

Supported FPGA platforms:


Package contents

 

nxMAC + nxPCS IP Core
– Libraries for functional simulation
– Synthesizable VHDL and Verilog RTL (encrypted) for synthesis/implementation

 

nxMAC + nxPCS Testbench
– Simulation libraries

 

Client-Server Reference Designs
– Simulation environment and scripts
– Quartus II and Vivado Synthesis/implementation project for supported partner’s boards

 

Complete Documentation
– User’s manual
– Getting started guide

 

Technical Support and Maintenance Updates
– 1 year of technical support
– 1 year of IP updates

Enyx certified board partners:


Available reference designs

 

Xilinx Virtex UltraScale +

 

Intel Stratix V

 

Intel Arria 10

Download

 

fact sheet

 

Are you already a customer ?

 

Get the latest IP Core release from Enyx Distribution Platform