Designed to efficiently build & maintain ultra-low latency FPGA applications for the financial industry

What is nxFramework?

The Enyx Development Framework (nxFramework) is a hardware and software development environment designed to efficiently build and maintain ultra-low latency FPGA applications for the financial industry.


Based on 10 years of research and development, nxFramework is the foundation for all Enyx off-the-shelf solutions and provides clients with the toolchain to manage a large portfolio of applications.


Developed for building in-house high performance trading engines, order execution systems, pre-trade risk check gateways, and custom projects — nxFramework offers:


nxFramework product diagram

What types of IP cores are included?

Connectivity & Utility cores


Ultra-low latency connectivity cores Latency
10G MAC/PCS  29 ns RTT – SOP to SOF @322MHz
35 ns RTT – SOP to SOP @322MHz

Includes 27.345 ns Xilinx VUS+ PMA 
40G MAC/PCS 55 ns RTT – SOP to SOF @322MHz
10G full TCP stack 53 ns RTT @322MHz
10G full UDP stack 43 ns RTT @322MHz
PCIe streaming DMA 790 ns RTT @250MHz


Library of 60+ utility cores
» MMIO core library
» Packet streaming core library
» Memory management core library
» Math core library
» Statistics core library
» Simulation helpers library


» Additional features:

In addition to the IP cores above, the Enyx development framework also provides the following elements:


  • Board Support Package: Platform-specific IP cores such as I²C controller, UART, QSPI flash controller, and Board Management Controller (BMC) are included
  • FPGA communication and IP core management via drivers, C/C++ libraries which support a variety of Linux distributions
  • Python scripts to manage development flow from synthesis to bitstream and includes a simulation environment

Performance Reports

Consult our latest latency figures


view report

Who should use nxFramework?

Any skilled FPGA developer starting a new low latency project, maintaining an existing one, or looking to change platforms can immediately reduce their time-to-production.


Our platform agnostic solution allows for mobility from one platform to another with minimal effort and can support designs across multiple different hardware platform vendors.


» Common use cases:

  • Market data processing engine
  • Inbound pre-trade risk gateway
  • Outbound order execution gateway
  • Tick-to-trade electronic trading platform
  • Financial data distribution application
  • Smart order router

Typical Client Profiles

View our partners

Utility cores

» MMIO core library

A collection of 8 utility cores to create memory mapped interfaces:


  • Splitter: A 1-to-N memory mapped bus splitter. Supports clock domain crossing
  • Slave: Translates MMIO request to register access. Supports read and write of registers of 32 bit width
  • CPU Master: A fully synthesizable CPU used to generate and execute commands on the MMIO bus supporting 20 instructions such as read_regwait_regwaitcompare, and  jump.  Primarily used for test benches or example designs to auto-configure a demonstration system without software
  • MM-to/from-ST: These cores convert a streaming interface to/from a register interface accessible by an MMIO interface via a simple protocol to read or send packets

» Packet streaming core library

A collection of 40 utility cores that provide basic operations for the packet streaming bus, mostly with zero latency. All cores can be configured with an additional pipe at their output.


The packet stream core library includes over 40 utility cores such as:


  • Add: Adds data of size bit_count at location bit_index in an Avalon ST packet
  • Align: Aligns an Avalon ST packet to a specified byte index removing all previous bytes
  • Arbitrate: Fully configurable arbiter (N-streams-to-1) using round robin or lowest ID first algorithms
  • Delay: Takes an Avalon ST packet as input and outputs the Avalon ST after configurable delay + random jitter
  • Drop: Drops an Avalon ST packet according to the input in_drop
  • Extract: Extracts a data of size bit_count at location bit_index in an Avalon ST packet
  • FIFO: Fully configurable streaming FIFO supporting single and dual clocks, store and forward, drop behavior management, packet size and checksum compute as well as providing statistics over MMIO
  • Merge: Merges multiple packets into one packet on the bus.
  • Pad: Pads an Avalon ST with zeros
  • Remove: Removes bytes of size bit_count at location bit_index from an Avalon ST packet
  • Replace: Replaces bytes in an Avalon ST packet
  • Size: Calculates the size in bytes of a packet and outputs it on EOP
  • Split: Splits an Avalon ST packet into several Avalon ST packets according to the in_split_size value
  • Truncate: Truncates an Avalon ST packet to a configurable length

» Memory management core library

A collection of 8 utility cores to store information including:


  • Content Addressable Memory: Generic single-cycle latency CAM using registers as memory with configurable internal pipelines.
  • FIFO: Fully configurable FIFO supporting single and dual clock, show-ahead and zero latency mode. Can use registers, distributed, block RAM based on configuration.
  • Hashtable: Generic hashtable with configurable hashing function and memory (FPGA internal or external) supporting find, add, remove, replace functions. Supports parallel hashing functions to reduce collisions.

» Math core library

A collection of 8 utility cores that provide math functions including:


  • CRC32 compute: Compute different types of CRC32 of an Avalon ST packet
  • Reed Solomon encoder/decoder: Low-latency Reed Solomon encoder and decoder IP cores to implement FEC
  • Multiplier: Platform and FPGA vendor agnostic multiplier function supporting signed and unsigned with configurable latency. Both LUT and DSP blocks can be used.
  • Division: Platform and FPGA vendor agnostic division function supporting configurable latency. Users can choose between Euclidean or Newton Raphson algorithms.

» Statistics core library

A collection of 9 utility cores that generate live statistics in an FPGA design:


  • Counter manager: This core computes statistics for a streaming interface based on an identifier such as packet count, byte count, error count, and drop count.
  • Latency probes: Collection of cores that timestamps events at various points in an FPGA design, then generates a stream of events IDs/timestamps to external software through PCIe or Ethernet for further analysis.
  • Snooper: This core computes statistics for a streaming interface such as longest/shortest packet size, backpressure events, pause events, and shortest inter-packet gap.
  • Stats report: This core counts events (such as packets or latency events) and builds sorted range based statistics. A typical use case would be to report the number of packets from size 1 to 64 bytes, 65 to 128 bytes, 129 to 256 bytes etc.

» Simulation helpers library

A collection of 28 utility cores for building test benches and simulation environments:


  • BFM (Bus Functional Model): Provides a simulation model for MMIO bus, Ethernet, IPv4, TCP, and UDP.
  • Generic test bench: Configurable test bench to read input (such as network packets, MMIO commands or regular commands) and write outputs (packets or regular commands) to files. Provides automatic comparison of produced output with a reference output file. Supports binary, ASCII and pcap formats as input or output.
  • Latency report: This cores computes the latency between two streaming interfaces and outputs a CSV file with all event occurrences, including packet size and latency in nanoseconds for further analysis
  • Simulation FIFO: Behavioral model of a FIFO to be used in a testing and validation environment.

Runtime Software Stack



» enyx-cores

IP core high level functions library

enyx-cores is a software library that relies on enyx-hw for accelerator communication and provides higher level methods to configure, monitor and use the hardware IP cores that are part of nxFramework such as:

  • TCP and UDP networking stacks
  • Flash management
  • Board Management Controller (temperature, hardware health status)
  • I²C and UART MMIO bridge primitives

enyx-cores is a set of extendable software libraries providing a methodology and model to build functions on top of enyx-hw for custom built hardware cores.

» enyx-hw

Hardware communication library

enyx-hw is multilayer software library primarily providing all communication primitives to interact with an FPGA accelerator through abstracted interfaces for packet streaming and memory input/output. enyx-hw currently supports the following interfaces:


  • Enyx ULL PCIe DMA: enyx-hfp
  • Enyx hardware mocking interface which allows users to implement behavioral software models of accelerator applications which are essential for testing


enyx-hw also includes functionality for IP core tree discovery and register mapping to provide MMIO access via generated C/C++ classes representing each core.

Discovery of the FPGA accelerator internals searching for a specific core in the MMIO tree (e.g. TCP core) and access to exposed registers for reading or writing are just a few of the features provided by enyx-hw.


The library uses XML file descriptions of core memory maps to represent internal register structures. These XML files can be custom crafted to create user defined IP core mappings and generate C/C++ structures or mocking classes.

» enyx-hfp

ULL streaming DMA drivers & libraries

enyx-hfp provides a Linux drivers suite and software library to interact with Enyx HFP ultra low latency direct memory access (DMA). This library also provides kernel bypass data packet send and receive primitives in addition to memory read/write primitives. Binary tools are provided to allow for monitoring of DMA usage.


Linux drivers also provide support for standard network interfaces to allow network traffic from the FPGA to be processed as it would with a regular NIC through the kernel networking stack.

» Operating system support & maintenance

The Linux kernel driver provided by Enyx is tested and compatible with version 3.10 to 5.15 and is compatible with the latest kernel versions. It is delivered as DKMS source packages.

Enyx software libraries and tools are built using the C compiler provided with each supported distribution and packaged as RPM or DEB as applicable.


All Enyx libraries are written in C language, with C++ header-only bindings. This allows the end user to use a C/C++ compiler of their choosing to build applications which link to the Enyx libraries.

Hardware Development Environment

A Python scripted development environment is provided to help users simplify their development cycle.



» Project & component management

nxFramework is a collection of components that can be standalone IP cores or “sandboxes” that include the developer business logic while respecting defined generic interfaces.

  • Each component becomes part of an application project, defined by YAML files, that will then be implemented on an FPGA hardware platform.
  • A collection of scripts allow automated dependency management between components and provide seamless simulation and firmware generation.

» Business logic RTL or HLS coding

A user can choose to build their sandbox using RTL (SystemVerilog, Verilog or VHDL) or directly in C/C++ using HLS technologies from the targeted FPGA vendor.

  • Generic interfaces to/from each core accessible from the sandbox are provided and highly configurable.
  • Configuration of general application and the business logic interfaces such as Ethernet interfaces, PCIe streaming DMAs, network interfaces, memory controllers as well as clocks, IP core parameters, frequencies and connectivity between elements.

» Behavioral simulation

Simulation environments supporting Mentor ModelSim® and Aldec® RivieraPro are provided with highly configurable generic test benches.

  • Each component of nxFramework can define multiple test scenarios corresponding to a test bench with multiple input vectors.
  • A command is used to run a simulation for a specific component.
  • Necessary TCL scripts for the target simulator tool are automatically generated and allow for batch or GUI mode for any component.

» Target FPGA vendor automated project generation up to bitstream

Once an application is ready for implementation on an FPGA, project creation for Intel® Quartus or Xilinx® Vivado is automatically performed.

  • Required TCL scripts for the target vendor synthesis tool are generated and allow batch or GUI mode workflow from synthesis to firmware generation of sof/bit files when JTAG programming and RBF files for flash programming.

» Device programming, on-board testing & debugging

The FPGA hardware can be updated using the enyx-firmware-manager tool.  enyx-inspector can be used to perform live debugging of a running application as described below.

Supported Platforms

Manufacturer  Model 1G 10G 25G 40G
Arista 7130 L Series (VU7P-2)

  • 7130-48L, 7130-96L
  • 7130-48LS, 7130-96LS

Arista 7130 LB Series (VU9P-3)

  • 7130-48LB, 7130-96LB
  • 7130-48LBS, 7130-96LBS

Arista 7130 EB Series (VU9P-3)

  • 7130-48EB
  ✔     ✔
BittWare XUP-P3R

  • VU9P-2
  • VU9P-3
  ✔    ✔    ✔    ✔
BittWare XUP-VV8

  • VU9P-3
  • VU13P-2
  • VU13P-3
   ✔    ✔
Xilinx® Alveo™ U50
Xilinx® Alveo™ U55C
  ✔    ✔    ✔    ✔
Xilinx® Alveo™ U200
Xilinx® Alveo™ U250
  ✔    ✔    ✔    ✔


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Supported Operating Systems

Operating System Version FDK SDK
10.x   ✔   ✔
11.x   ✔   ✔
 7.x   ✔   ✔
 8.x   ✔   ✔
 18.04 (LTS)   ✔   ❌
 20.04 (LTS)   ✔   ✔
 22.04 (LTS)   ❌   ✔
 MOS 0.36.6   ❌   ✔