published on 01/04/2022
FPGA Design Engineer
ENYX-2022-HW-DEV-Montreal
Full time
Min 3 years
Degree in Electronic Engineering
Base + Variable
The company
At Enyx, our goal is to lead the way as the finance industry embraces more advanced technology in its pursuit towards building more comprehensive, efficient and fair infrastructures.
We believe that the benefits of FPGA technology can be accessible to a wider group of end-users with a range of diverse needs and problems to solve.
Behind our products, we have a talented, dedicated, and passionate team split between Paris, New York, Montréal, London and Hong Kong.
Job description
Enyx is looking to build an engineering office in the province of Québec, in the Montreal region. We are looking to start with applicants interested in a Full Time job based in a coworking place with growth expectations.
What you’ll do
Developing hardware and software, our Technology team creates and maintains the low-latency ASIC/FPGA HDL building blocks for the ensemble of Enyx products as part of the nxFramework FDK (Firmware Development Kit).
You will take part in the hardware implementation of system protocols such as TCP or MAC/PCS at different speeds as well as applications based on those IPs. These hardware components are used internally at Enyx by the product and solution teams and part of the nxFramework FDK used by various large financial institutions to build FPGA accelerated applications. You will be working with high end FPGA boards and switches targeted for ultra low latency applications.
You will work on all phases of the project to guarantee an optimized, performing architecture that responds to the constraints of ASIC and FPGA development.
Your main responsibilities will be to :
- Participate on the development cycle from RTL coding up to solution test automation on actual ASIC/FPGA boards
- Ensure performance evolvability and maintenance
- Ensure code quality, coverage and unit testing
- ATechnology surveillance to understand and adapt to the evolving stakes
Applicant profile
Your qualifications & experience
- Degree in Electronic Engineering
- At least 3 years of professional experience
- Full understanding of the complete FPGA flow with knowledge in timing analysis
- An experience in ASIC development and verification would be a plus
- An excellent technical level in VHDL or Verilog allowing to judge the quality, maintainability and performance of the HDL building blocks
- Technical environment: FPGA, ASIC, VHDL, Verilog, Vivado, TCP, UDP, PCIe, DMA, Network, Python, Linux, GIT, Jenkins
- Professional English and French
- You have a desire to understand high performance and low latency solutions in a competitive trading industry
- You are passionate about working on very technical and innovative products
- You have a dynamic and rigorous work-ethic with the ability to work in a team-oriented, technical, collaborative environment
- You like to be involved in technical subjects and contributing to solve problems, be it in a team or managing issues/troubleshooting
- You are a critical thinker, life-long learner and enjoy discovering new technologies and solutions
- You enjoy working with people in a good mood
What’s in it for you
- You’ll be an integral member of a team where you will help define the product direction
- You’ll have an opportunity to challenge yourself and avoid the status quo with a goal of quality, performance and operational excellence
- We offer perks that will help you find your work-life balance and professional comfort:
- flexibility in working hours
- dedicated budget for your IT-comfort
- a minimum of two trips per year to our Headquarters in Paris, France to meet the team and mingle
- top health coverage
- RRSP with up to 4% employee match
- 4 weeks of Paid Time Off + Sick & Personal days
Our process
- Apply and first contact with Ana - Our Recruitment Manager
- Interview with Vincent - Your future Technical Team Manager
- Interview with Christophe - Our CTO Hardware
- Debriefing with Ana
- Offer
We are equal opportunity and value diversity - We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, or disability status."
Location
417 Rue Saint-Pierre, Suite 401, Montréal, QC, H2Y 2M4, Canada
417 Rue Saint-Pierre, Suite 401, Montréal, QC, H2Y 2M4, Canada
Keywords
FPGA
ASIC
VHDL
Verilog
Vivado
TCP
UDP
PCIe
DMA
Network
Python
Linux
GIT
Jenkins
Interested in a career with Enyx?
Please click on the button below to apply for this position.