Enyx, a leading developer of high performance trading solutions for the financial industry, has launched a new version of nxFramework


An FPGA-based development framework designed to reduce time-to-production when developing ultra-low latency trading systems, nxFramework achieves this efficiency through the standardization of core IP blocks needed to build any FPGA-based trading platform — enabling developers to focus on optimizing their business logic.


As the foundation for all Enyx off-the-shelf solutions, nxFramework provides users with the toolchain to create and manage a large portfolio of applications, such as pre-trade risk check gateways, smart order routers, and tick-to-trade electronic trading platforms.


This latest release, which is now available to all nxFramework subscribers, features a new 40G MAC/PCS ultra-low latency core and added support for 40G with the Enyx TCP Standard Edition core. Subscribers of nxFramework are now able to build low latency FPGA designs compatible with exchanges that provide 40G native connectivity.


An ultra-low latency 10G UDP stack was also added to version 5.4 of nxFramework allowing subscribers to have an off-the-shelf low latency UDP stack that can be included in their designs—further simplifying development efforts when trading with exchanges that provide a 10G UDP hand-off.


Additionally, improved latency benchmarks for both the Enyx 40G MAC/PCS IP and the Enyx 10G UDP Ultra Low Latency stack are included. The latency figures are as follows:


    • 55 ns RTT – SOP to SOF @322MHz
    • 61 ns RTT – SOP to SOP @322MHz

(Includes 27.345 ns Xilinx VUS+ PMA)


  • 10G UDP ULL stack 
    • 43 ns RTT – SOP to SOP @322MHz


Along with these latency improvements, the following update was included:


    • SmartNIC example configurations of nxFramework using the 10G UDP ULL stack.


Check out all of our nxFramework latency reports on our Enyx Performance Reports page.


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