June 7, 2021 | Product Update
Enyx releases new version of nxFramework that includes significant latency reductions and additional features
An FPGA-based development framework designed to reduce time-to-production when developing ultra-low latency trading systems, nxFramework achieves this efficiency through the standardization of core IP blocks needed to build any FPGA-based trading platform — enabling developers to focus on optimizing their business logic.
As the foundation for all Enyx off-the-shelf solutions, nxFramework provides users with the toolchain to create and manage a large portfolio of applications, such as pre-trade risk check gateways, smart order routers, and tick-to-trade electronic trading platforms.
The latest version of nxFramework adds support for the Bittware XUP-VV8 FPGA board, expanding platform options available to developers. Additionally, this release includes connectivity core improvements to reduce latency and features new tools that help simplify development efforts.
A key new feature is the inclusion of jitter cleaners for the Bittware XUP-VV8 platform. They enable the support of synchronous ethernet, a key component for end-users with ULL strategies. Jitter cleaners allow the in/out datapath to run at the same frequency on the FPGA — eliminating the need for Clock Domain Crossing (CDC) and reducing overall latency.
This latest release includes improved latency benchmarks for both the Enyx 10G MAC/PCS IP and the Enyx 10G TCP Ultra Low Latency stack. The new latency figures are as follows:
- 27 ns RTT – SOP to SOF @322MHz
- 33 ns RTT – SOP to SOP @322MHz
(Includes 17.26 ns Xilinx VUS+ PMA)
- 53 ns RTT – SOP to SOP @322MHz
Along with these latency improvements provided as part of the upgrade, nxFramework clients receive additional features – including:
- Enyx 10G TCP stack with ‘Capture Mode’ — a new feature that allows the user to monitor in/out traffic of the TCP stack for efficient troubleshooting and debugging
- A new code generation tool designed to simplify collaboration between software and hardware engineers
- Added support for clock jitter cleaners
- An updated Enyx SmartNIC reference design that now instantiates the TCP and UDP stacks on separate Ethernet ports
Check out all of our nxFramework latency reports on our Enyx Performance Reports page.
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