Enyx, a leader in ultra-low latency FPGA-based technology and solutions, is proud to announce the addition of an HLS development framework for nxAccess — Enyx’s ultra low-latency Market Access solution.


Designed to improve the time-to-market of a full FPGA tick-to-trade solution, the nxAccess HLS framework allows software engineers to autonomously develop, test and deploy full hardware algorithms using Xilinx Vivado HLS technology.


The Challenges:

Trading environments are becoming more difficult to master due to ever increasing data volumes and rapidly evolving technology —  driving the need for improved determinism and lower latencies.


Modernizing your trading infrastructure with FPGA technology can help overcome these issues, but a few challenges remain:

✓  Increased time-to-market

  • FPGA development is complex, time consuming and requires special expertise to successfully complete
✓  Venue support & EDC management

  • Scaling FPGA trading operations to access more venues while keeping up with frequent protocol updates is more difficult in hardware
✓  One platform for all strategies

  • Using different solutions for trading strategies with varying latency requirements increases overall complexity, risk, and cost
✓  Monitoring & reporting system integration

  • Often overlooked, it is crucial that FPGA solutions are seamlessly integrated into existing monitoring and reporting systems


What is nxAccess – The Enyx Market Access Solution?


NxAccess is Enyx’s latest FPGA-powered, end-to-end market access solution providing the ability to consume market data and send orders both from a hardware and a software algorithm.


To accomplish this, nxAccess leverages the speed and determinism of an FPGA to fully process, filter and normalize raw market data.


Additionally, nxAccess can preload up to 16,384 individuals orders or groups of orders within the FPGA’s memory to significantly reduce latency compared to legacy software solutions.


The nxAccess solution offers added flexibility by now supporting trading algorithms developed using Higher Level Synthesis (HLS) technologies, in addition to traditional hardware native languages such as VHDL or Verilog — making ultra low latency trading strategies more accessible to clients.




The Solution: The nxAccess HLS framework


The nxAccess HLS development framework allows customers to develop their own FPGA-enabled trading algorithms using HLS, a C-like programming language, and Xilinx Vivado suite.

Combining the ultra low latency of the Enyx FPGA feed handler and order execution gateway, clients with the most latency sensitive strategies can now code their trading algo directly in the FPGA.


The Enyx HLS framework makes FPGAs more accessible to software developers and non-FPGA experts


Using this framework, software engineers can develop, test and deploy trading strategies onto the nxAccess’s FPGA. Following the workflow described below, nxAccess facilitates the development, simulation and deployment of proprietary trading logic inside the FPGA.





Key Benefits:

  Reduced time-to-market

  • nxAccess includes a full hardware feed handler and execution gateway, so the only thing missing is your trading algorithm
✓  Easy to scale

  • Thanks to broad market coverage and normalized software and hardware interfaces, expanding to new venues has never been easier
✓  One platform for all strategies

  • Able to power both hardware and software strategies, the nxAccess platform is a standardized market access solution
✓  Monitoring & reporting system integration

  • Monitoring tools with embedded error and system notifications ensure that nxAccess can easily integrate into any existing infrastructure


Key Features:

  • A simple C++ API enables the trading application to configure the embedded hardware feed handler, receive accurate market data updates, prepare and preload orders into the execution engine.
  • Continuous interactions with the hardware trading logic allows the trading application to monitor and update the trading parameters.
  • Customers without in-house hardware expertise can adapt their latency sensitive strategies to run directly on the FPGA with a sub 800 ns tick-to-trade latency.
  • Standardized interfaces enable the client to implement their trading strategies interchangeably across different exchange protocols, allowing for increased scalability.


Latency Profile :


* Maximums are due to the 10Gbs throughput limit causing queuing of orders when several orders are sent at once



Want to learn more?


Feel free to reach out if you have any questions or if you want to setup an introductory phone call.


Please find links to all our nxAccess HLS documentation here:


HLS Product Brief

Presentation Slides

HLS Demo

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